Conventional datacenter computing systems use various components that are generally known in the art. For instance, such systems typically include an assembly of servers with processors, memory, etc. in which standard buses and input/output (I/O) controllers are typically deployed. Recent trends favor larger memory provisioning for database, in-memory-processing, and low latency system responses. It is desired that non-volatile memory (NVM) technology may someday support low latency applications (200 nanoseconds (ns) to 400 ns readouts), which may be used in Storage Class Memory (SCM) solutions, and/or, in multiprocessor systems, where NVM may be used as shared-memory. Relative to Dynamic Random Access Memory (DRAM), however, conventional NVM systems, such as Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), and Magnetoresistive Random Access Memory (MRAM), have several limitations. For instance, conventional NVM systems (a) are orders of magnitude more energy demanding than DRAM to write a bit; (b) have finite endurance as opposed to the virtually infinite endurance of DRAM; and (c) have an undesirable error rate immediately after fabrication (e.g., raw Bit Error Rate (BER) of NVM systems are approximately 1E-5 or 1E-6, whereas “error-free” operation would require an Uncorrectable Bit Error Rate (UBER)<1E-18).
Accordingly, it would be desirable to provide a system and method which overcomes these limitations. To this end, it should be noted that the above-described deficiencies are merely intended to provide an overview of some of the problems of conventional systems, and are not intended to be exhaustive. Other problems with the state of the art and corresponding benefits of some of the various non-limiting embodiments may become further apparent upon review of the following detailed description.